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STV0042A satellite sound and video processors march 1997 product preview shrink42 (plastic package) order code : STV0042A sound . two independent sound demodulators . pll demodulation with 5-10mhz frequency synthesis . programmable fm demodulator bandwidth accomodating fm devia- tions from 30khz till 400khz . programmable 50/75 m s or no de-em- phasis . dynamic noise reduction . one or two auxiliary audio inputs and outputs . gain controlled and muteable audio outputs . high impedance mode audio outputs for twin tuner applications video . composite video 6-bit 0 to 12.7db gain control . composite video selectable in- verter . two selectable video de-emphasis networks . 4 x 2 video matrix . high impedance mode video outputs for twin tuner applications miscellaneous . 22khz tone generation for lnb control . i 2 c bus control : chip addresses = 06 hex . low power stand-by mode with active audio and video matrixes description the STV0042A bicmos integrated circuit realizes all the necessary signal processing from the tuner to the audio/video input and output connectors regardless the satellite system. the stv0042 is intended for low cost satellite receiver application. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 a gnd r fc l pk out i ref cpump r u75 r det r amplk r a 12v a 12v v ref a gnd l agc r amplk l u75 l det l cpump l gnd 5v v dd 5v xtl sda scl agc l fm in s2 rtn r s2 rtn l b-band in v gnd clamp in videem1 v 12v videem2/22khz uncl deem s2 out r s2 out l s2 vid rtn vol l s2 vid out s1 vid out vol r sum out pk in fc r 0042a-01.eps pin connections 1/24
pin assignment pin number name function 1 fc r audio roll-off right 3 sum out noise reduction summing output 2 pk in noise reduction peak detector input 4 vol r volume controlled audio out right 5 s1 vid out tv-scart 1 video output 6 s2 vid out vcr-scart 2 video output 7 vol l volume controlled audio out left 8 s2 vid rtn vcr-scart 2 video return 9 s2 out l fixed level audio output left 10 clamp in sync-tip clamp input 11 s2 out r fixed level audio output right 12 uncl deem unclamped deemphasized video output 13 videem2/22khz video deemphasis 2 or 22khz output 14 v 12v video 12v supply 15 videem1 video deemphasis 1 16 v gnd video ground 17 b-band in base band input 18 s2 rtn l auxiliary audio return left 19 s2 rtn r auxiliary audio return right 20 fm in fm demodulator input 21 agc l agc peak detector capacitor left 22 scl i 2 c bus clock 23 sda i 2 c bus data 24 xtl 4/8mhz quartz crystal or clock input 25 v dd 5v digital 5v power supply 26 gnd 5v digital power ground 27 cpump l fm pll charge pump capacitor left 28 det l fm pll filter left 29 u75 l deemphasis time constant left 30 amplk l amplitude detector capacitor left 31 agc r agc peak detector capacitor right 32 a gnd l audio ground 33 v ref 2.4v reference 34 a 12v audio 12v supply 35 amplk r amplitude detector capacitor left 36 det r fm pll filter right 37 u75 r deemphasis time constant right 38 cpump r fm pll charge pump capacitor right 39 i ref current reference resistor 40 pk out noise reduction peak detector output 41 fc l audio roll-off left 42 a gnd r audio ground 0042a-01.tbl STV0042A 2/24
pin description 1 - sound detection fmin this is the input to the two fm demodulators. it feeds two agc amplifiers with a bandwidth of at least 5-10mhz. there is one amplifier for each channel both with the same input. the agc ampli- fiers have a 0db to +40db range. z in =5k w , min input = 2mv pp per subcarrier. max input = 500mv pp (max when all inputs are added together, when their phases coincide). agc l, agc r agc amplifiers peak detector capacitor connec- tions. the output current has an attack/decayratio of 1:32. that is the ramp up current is approxi- mately 5 m a and decay current is approximately 160 m a. 11v gives maximum gain. these pins are also driven by a circuit monitoring the voltage on amplk l and amplk r respectively. amplk l, amplk r the outputs of amplitude detectors left and right. each requires a capacitor and a resistor to gnd. the voltage across this is used to decide whether there is a signal being received by the fm detector. the level detector output drives a bit in the detector i 2 c bus control block. amplk l and amplk r drive also respectively agc l and agc r. for instance when the voltage on amplk l is > (v ref +1v be ) it sinks current to v ref from pin agcl to reduce the agc gain. det l, det r respectively the outputs of the fm phase detector left and right. this is for the connection of an external loop filter for the pll. the output is a push-pull current source. cpump l, cpump r the output from the frequency synthesizer is a push-pullcurrent source which requiresa capacitor to ground to derive a voltage to pull the vco to the target frequency. the output is 100 m a to achieve lockand 2 m a during lock to provide a trackingtime constant of approximately 10hz. vref this is the audio processor voltage reference used through out the fm/audio section of the chip. as such it is essential that it is well decoupled to ground to reduce as far as possible the risk of crosstalk and noise injection. this voltage is de- rived directly from the bandgap reference of 2.4v. the v ref output can sink up to 500 m a in normal operation and 100 m a when in stand-by. iref this is a bufferedv ref outputto an off-chip resistor to produce an accurate current reference, within the chip, for the biasing of amplifiers with current outputs into filters. it is also required for the noise reduction circuit to provide accurate roll-off fre- quencies. this pin should not be decoupled as it would inject current noise. the target current is 50 m a 2% thus a 47.5k w 1% is required. a 12v double bonded main power pin for the audio/fm section of the chip. the two bond connections are to the esd and to power the circuit and on chip regulators/references. a gnd l this ground pin is double bonded : 1) to channel left : rf section & vco, 2) to both agc amplifiers, channel left and right audio filter section. a gnd r this ground pin is double bonded : 1) to the volume control, noise reduction system, esd + mux + v ref 2) to channel right : rf section & vco 2 - baseband audio processing pk out the noise reduction control loop peak detector output requires a capacitor to ground from this pin, and a resistor to v ref pin to give some accurate decaytime constant.an on chip5k w 25 % resistor and external capacitor give the attack time. pk in this pin is an input to a control loop peak detector and is connectedto the output of the offchip control loop band pass filter. sum out the two audio demodulated signals are summed together by means of an amplifier with a gain of 0.5. if both inputs are 1v then the output is 1v. this amplifier has an input follower buffer which gives a v be offset in the dc bias voltage. thus the filter which this amplifier drives must include ac cou- pling to the next stage (pk in pin). fc l, fc r the variable bandwidth transconductance ampli- fier has a current output which is variable depend- ing on the input signal amplitude as defined by the control loop of the noise reduction. the output current is then dumped into an off-chip capacitor which together with the accurate current reference define the min/max rolloff frequencies.a resistor in series with a capacitor is connected to ground from these two pins. STV0042A 3/24
u75 l, u75 r external deemphasis networks for channels left and right. for each channel a capacitor and resistor in parallel of 75 m s time constant are connected between here and v ref to provide 75 m s de-emphasis.internally selectable is an internal resistor that can be pro- grammed to be addedin paralleltherebyconvertingthe networkto approx50 m s de-emphasis(see controlblock map).the value of the internal resistors is 30k w 30%. theamplifier forthisfilterisvoltageinput,currentoutput; with 500mv input the outputwill be 55 m a. vol l, vol r themain audiooutputfrom thevolume controlamplifier the signal to get output signals as high as 2v rms (+12db)on a dcbias of 4.8v.controlis from +12dbto -26.75db plus mute with 1.25db steps. this amplifier has short circuit protection and is intended to drive a scart connector directly via ac coupling and meets thestandardscartdriverequirements.theseoutputs feature high impedance mode for parallel connection. s2 out l, s2 out r these audio outputs are sourced directly from the audiomux, and as a result do not include any volume controlfunction.theywill outputa 1v rms signalbiased at4.8v.they are shortcircuit protected.these outputs feature high impedance mode for parallel connection and meetscart drive requirement. s2 rtn l, s2 rtn r these pins allow auxiliary audio signals to be con- nected to the audio processor and hence makes use of the on-chip volume control. for additional details please refer to the audio switching table. 3 - video processing b-band in ac-coupled video input from a tuner. z in >10k w 25%. this drives an on-chipvideo ampli- fier.theotherinputofthisampisacgroundedbybeing connectedto an internal v ref . the video amplifier has selectablegain from 0dbto 12.7dbin 63 stepsand its output signal can be selected normal or inverted. uncl deem deemphasized still unclamped output. it is also an input of the video matrix. videem1 connected to an external de-emphasis network (for instance 625 lines pal de-emphasis). videem2 / 22khz connected to an external de-emphasis network (for instance 525 lines ntsc or other video de-em- phasis).alternatively a precise 22khz tone may be output by i 2 c bus control. clamp in this pin clampsthemost negativeextremeof theinput (the sync tips) to 2.7v dc (or appropriate voltage). the video at the clamp input is only 1v pp . this clamped video which is de-emphasised, filtered and clamped (energydispersalremoved) is normal, negative syncs, video. this signal drives the video matrix input called normal video. it has a weak (1.0 m a 15 %) stable current source pulling the input towards gnd. other- wise the input impedance is very high at dc to 1khz z in >2m w . video bandwidth through this is -1db at 5.5mhz. the clamp input dc restore voltageis then usedas a means forgettingthecorrect dc voltageon the scart outputs. s2 vid rtn external video input 1.0v pp ac coupled 75 w source impedance. this input has a dc restoration clamp on its input. the clamp sink current is 1 m a 15% with the buffer z in >1m w . this signal is an input to the video matrix. s1 vid out, s2 vid out videodrivers for scart 1 and scart 2. an external emitter follower bufferis required to drive a 150 w load. the average dc voltage to be 1.5v on the o/p. the signalis video2.0v pp 5.5mhzbw with synctip = 1.2v. these pins get signals from the video matrix. the signalselected from the video matrix for outputon this pin is controlled by a control register. this output also featurea highimpedancemodeforparallelconnection. v 12v +12v double bonded : esd+guard rings and video circuit power. v gnd doubled bonded. clean vid in gnd. strategically placed video power ground connection to reduce video currents getting into the rest of the circuit. 4 - control block gnd 5v the main power ground connection for the control logic, registers, the i 2 c bus interface, synthesizer & watchdog and xtlosc. vdd 5v digital +5v power supply. scl this is the i 2 c busclock line. clock = dc to 100khz. requires external pull up eg. 10k w to 5v. sda this is the i 2 c bus data line. requires external pull up eg. 10k w to 5v. xtl this pin allows for the on-chip oscillator to be either used with a crystal to ground of 4mhz or 8mhz, or to be driven by an external clock source. the external source can be either 4mhz or 8mhz. a programmablebit in the control block removes a 2 block when the 4mhz option is selected. pin description (continued) STV0042A 4/24
STV0042A b-band video processing 4x2 video matrix 2 2 from tuner audio matrix + volume fm demodulation 2 channels from tuner noise reduction + deemphasis 1 i 2 c bus interface from vcr/decoder 22khz to lnb 2 2 to tv, vcr/decoder active in stand-by 0042a -02.eps general block diagram clamp clamp normal vcr / decoder return to decoder or vcr to tv s1 vid out s2 vid out s2 vid rtn clamp in g b-band in STV0042A 22khz tone baseband lpf videem1 videem2/22khz uncl deem ntsc pal deemphasized 1 17 13 15 12 5 6 8 10 2 0042a-03.eps video processing block diagram STV0042A 5/24
STV0042A pk out pk in sum out fc l audio deemphasis s2 rtn r u75 r det r pll filter 5 k3 k2 a k1 a c b bc k5 mono stereo s2 out r vol r tv audio r anrs decoder or vcr a b 36 19 40 2 3 1 41 37 11 4 6db fc r -6db 0042a-04.eps audio processing block diagram (channel right) STV0042A pk out pk in sum out fc l audio deemphasis s2 rtn l u75 l det l pll filter 5 k3 k2 a k1 a c b bc k5 mono stereo s2 out l vol l tv audio l anrs decoder or vcr a b 28 18 40 2 3 1 41 29 9 7 6db fc r -6db 0042a-05.eps audio processing block diagram (channel left) STV0042A 6/24
audio deemphasis + anrs vol out aux out audio pll aux in k 1a k 5b k 5c k 5a k 1c 0042a-06.eps audio switching k 2 k 3 a b 1 b 2 on on on no anrs, no de-emphasis no anrs, 50 m s no anrs, 75 m s a b 1 b 2 off off off anrs, no de-emphasis anrs, 50 m s anrs, 75 m s agc level detector 1 level detector 2 fm in agc r amplk r v ref reg8 b4 bias 90 0 vco audio r det r cpump r synthesizer STV0042A amp. detect sw1 phase detect v ref fm dev. select. sw4 sw2 agc level detector 1 level detector 2 agc l amplk l v ref bias 90 0 vco audio l det l cpump l amp. detect sw3 phase detect v ref fm dev. select. watchdog watchdog reg8 b0 0042a-07.eps fm demodulation block diagram STV0042A 7/24
circuit description 1 - video section the composite video is first set to a standard level by means of a 64 step gain controlled amplifier. in the casethat themodulationis negative,an inverter can be switched in. one of two different external video de-emphasis networks (for instance pal and ntsc) is select- able by an integrated bus controlled switch. then energy dispersal is removed by a sync tip clamping circuit, which is used on all inputs to a video switching matrix, thus making sure that no dc steps occur when switching video sources. the matrix can be used to feed video to and from decoders, vcr's and tv's. additionaly all the video outputs are tristate type (high impedance mode is supported), allowing a simple parallel connections to the scarts (twin tuner applications). 2 - audio section the two audio channels are totally independentex- cept for the possibility given to output on both chan- nels only one of the selected input audio channels. to allow a very cost effective application, each channel uses pll demodulation. neither external complex filter nor ceramic filters are needed. the frequency of the demodulated subcarrier is chosen by a frequency synthesizer which sets the frequency of the internal local oscillator by com- paring its phase with the internally generated reference. when the frequency is reached, the microprocessor switches in the pll and the de- modulationstarts. atany moment the microproces- sor can read from the device (watchdog registers) the actual frequency to which the pll is locked. it canalso verify that a carrier is present at the wanted frequency(by reading amplk status bit) thanks to a synchronous amplitude detector, which is also used for the audio input agc. in order to maintain constant amplitude of the recovered audio regardless of variations between satellites or subcarriers, the pll loop gain may be programmed from 56 values. any frequency deviation can be accomodated (from 30khz till 400khz). in the typical application, the STV0042A offers two audio de-emphasis 75 m s and 50 m s. when required a j17 de-emphasis can be implemented by using specific applicationdiagram (see application note : an838, chapter 4.2). a dynamic noise reduction system (anrs) is inte- grated into the STV0042A using a lowpass filter, the cut-off frequency of which is controlled by the amplitude of the audio after insertion of a band- pass filter. two types of audio outputs are provided : one is a fixed 1v rms and the other is a gain controlled 2v rms max. the control range being from +12db to -26.75dbwith 1.25db steps. this output canalso be muted. a matrix is implemented to feed audio to and from decoders vcr's and tv's. noise reduction system and de-emphasis can be inserted or by-passed through bus control. also all the audio outputs are tristate-type (high impedance mode is supported), allowing a simple parallel connections to the scarts (twin tuner applications). 3 - others a 22khz tone is generated for lnb control. it is selectable by bus control and available on one of the two pins connected to the external video de-emphasis networks. by means of the i 2 c bus there is the possibility to drive the ics into a low power consumption mode with active audio and video matrixes. inde- pendantly from the main power mode, each indi- vidual audio and video output can be driven to high impedance mode. STV0042A 8/24
absolute maximum ratings symbol parameter value unit v cc v dd supply voltage 15 7.0 v v p tot total power dissipation 900 mw t oper operating ambient temperature 0, + 70 o c t stg storage temperature -55, + 150 o c 0042a-02.tbl thermal data symbol parameter value unit rth(j-a) thermal resistance junction-ambient 60 o c/w 0042a-03.tbl dc and ac electrical characteristics (v cc = 12v, v dd =5v,t amb =25 o c unless otherwise specified) symbol parameter test conditions min. typ. max. unit v cc v dd sypply voltage 11.4 4.75 12 5.0 12.6 5.25 v v iq cc iq dd supply current all audio and all video outputs activated 55 8 70 15 ma ma iqlp cc iqlp dd supply current at low power mode all audio and all video outputs are in high impedance mode 27 6 35 9 ma ma audio demodulator fmin fm subcarrier input level (pin fmin for agc action) vco locked on carrier at 6mhz 560k w load on amplock pins 180k w load on det pins 5 500 mv pp deth detector 1 and 2 (amplock pins) (threshold for activating level detector 2) 8mv pp fmin 500mv pp carrier without modulation 2.90 3.10 3.30 v vcomi vco mini frequency v cc : 11.4 to 12.6v, t amb : 0 to 70 o c 5 mhz vcoma vco maxi frequency 10 mhz ap50 1khz audio level at pll output (det pins) 0.5v pp 50khz dev. fm input, coarse deviation set to 50khz (reg. 05 = 36 hex ) 0.6 1 1.35 v pp apa50 1khz audio level at pll output (det pins) 0.5v pp 50khz dev. fm input, coarse and fine settings used 0.92 1 1.08 v pp fmbw fm demodulator bandwidth gain at 12khz versus 1khz 180k w , 82k w 22pf on det pins 0 0.3 1 db dpco digital phase comparator output current (cpump pins) average sink and source current to external capacitor 60 m a automatic noise reduction system lrs output level (pin sumout) 1v pp on left and right channel 0.9 1 1.1 v pp ldor level detector output resistance (pins pk out) 4.0 5.4 6.8 k w ndft level detector fall time constant (pins pk out) external 22nf to gnd and 1.2m w to v ref 26.4 ms ndll bias level (pins pk out) no audio in 2.40 v llcf noise reduction cut-off frequency at low level audio 100mv pp on det pins, external capacitor 330pf (fc pins) 0.85 khz hlcf noise reduction cut-off frequency at high level audio 1v pp on det pins, external capacitor 330pf (fc pins) 7 khz 0042a-04.tbl STV0042A 9/24
dc and ac electrical characteristics (continued) (v cc = 12v, v dd =5v,t amb =25 o c unless otherwise specified) symbol parameter test conditions min. typ. max. unit audio output (pins vol out r, vol out l) dcol dc output level 4.8 v aoln audio output level with reg 00 = 1a fm input as for apa50 no de-emphasis, no pre-emphasis no noise reduction 1.5 1.9 2.34 v pp aol50 audio output level with reg 00 = 1a fm input as for apa50 50 m s de-emphasis, 27k w //2.7nf load no pre-emphasis, no noise reduction 2.0 3.3 4.0 v pp aol75 audio output level with reg 00 = 1a fm input as for apa50 75 m s de-emphasis, 27k w //2.7nf load no pre-emphasis, no noise reduction 2.0 3.3 4.0 v pp ama1 audio output attenuation with mute-on. reg 00 = 00. 1v pp - 1khz from s2 rtn pins 60 65 db mxat max attenuation before mute. reg 00 = 01. 1khz, from s2 rtn pins 32.75 db mxag audio gain. reg 00 = 1f. 1khz, from s2 rtn pins 5 6 7 db astp attenuation of each of the 31 steps 1khz 1.25 db thda1 thd with reg 00 = 1a 1v pp -1khz from s2 rtn pins 0.15 % thda2 thd with reg 00 = 1a 2v pp -1khz from s2 rtn pins 0.3 1 % thdfm thd with reg 00 = 1a fm input as for apa50 75 m s de-emphasis, anrs on 0.3 1 % acs audio channel separation 1v pp -1khz on s2 rtn pins 60 74 db acsfm audio channel separation at 1khz - 0.5 v pp - 50khz deviation fm input on one channel - 0.5v pp no deviation fm input on the other channel - reg 05 = 36 hex -75 m s de-emphasis, no anrs 60 db snfm signal to noise ratio fm input as for apa50, 75 m s de-emphasis, no anrs, unweighted 56 db snfmnr signal to noise ratio fm input as for apa50 75 m s de-emphasis, anrs on, unweighted 69 db z out l z out h audio output impedance low impedance mode high impedance mode 30 18 44 55 w k w auxiliary audio output (pins s2 out r, s2 out l) dcolao dc output level aux. input pins open circuit 4.8 v aolns audio output level on s2 fm input as for apa50 no de-emphasis, no pre-emphasis no noise reduction 1.55 2 2.42 v pp aol50s audio output level on s2 fm input as for apa50 50 m s de-emphasis, 27k w //2.7nf load no pre-emphasis, no noise reduction 2.0 3.4 4.0 v pp aol75s audio output level on s2 fm input as for apa50 75 m s de-emphasis, 27k w //2.7nf load no pre-emphasis, no noise reduction 2.0 3.4 4.0 v pp thdaofm thd on s2 fm input as for apa50 75 m s de-emphasis, no anrs 0.3 1 % z out l z out h audio output impedance low impedance mode high impedance mode 30 60 44 100 55 w k w 0042a-05.tbl STV0042A 10/24
dc and ac electrical characteristics (continued) (v cc = 12v, v dd =5v,t amb =25 o c unless otherwise specified) symbol parameter test conditions min. typ. max. unit reset rtccu end of reset threshold for v cc v dd = 5v, v cc going up 8.7 v rtccd start of reset threshold for v cc v dd = 5v, v cc going down 7.9 v rtddu end of reset threshold for v dd v cc = 12v, v dd going up 3.8 v rtddd start of reset threshold for v dd v cc = 12v, v dd going down 3.5 v composite signal processing vidc vid in external load current < 1 m a 2.25 2.45 2.65 v zvi vid in input impedance 7 11 14 k w deodc dc output level (pins videem) 2.25 2.45 2.65 v deomx max ac level before clipping (pins videem) gv = 0db, reg 01 = 00 2 v pp dgv gain error vs gv @ 100khz gv = 0 to 12.7db, reg 01 = 00 3f -0.5 0 0.5 db invg inverter gain -0.9 -1 -1.1 visog video input to scart output gain de-emphasis amplifier mounted in unity gain, normal video selected -1 0 1 db debw bandwidth for 1v pp input measured on pins videem @ - 3db with gv = 0db, reg 01 = 00 10 mhz dfg differential gain on sync pulses measured on pins videem gv = 0db, 1v pp cvbs + 0.5v pp 25hz sawtooth (input : vid in) 1% itmod intermodulation of fm subcarriers with chroma subcarrier 7.02 and 7.2mhz sub-carriers, 12.2db lower than chroma -60 db clamp stages (pins clamp in, s2) iskc clamp input sink current v in = 3v 0.5 1 1.5 m a iscc clamp input source current v in =2v 40 50 60 m a video matrix xtk output level on any output when 1v pp cvbs input is selected for any other output @ 5mhz -60 db bfg output buffer gain (pins s1 vid out, s2 vid out) @ 100khz 1.87 2 2.13 dcolvh dc output level high impedance mode 0 0.2 v z out hv video output impedance high impedance mode 16 23 30 k w vcl sync tip level on selected outputs (pins s1 vid out, s2 vid out) 1v pp cvbs through 10nf on input 1.05 1.3 1.55 v 0042a-06.tbl STV0042A 11/24
pin internal circuitry s2 vid rtn, clamp in 50 m a source is active only when vidin < 2.7v. 50 m a 1 m a 10k w s2 vid rtn clamp in v dd 5v gnd 0v 1 1 v dd 9v 0042a-08.eps figure 1 s1 vid out, s2 vid out same as above but with no black level adjustment. 2.3ma gnd 0v 4 v cc 12v vid mux 10k w 20k w gnd 0v 60 w s1 vid out s2 vid out v ref 2.4v 20k w 0042a-09.eps figure 3 uncl deem same as above but with no black level adjustment and slightly different gain. 2.3ma gnd 0v 4 v cc 12v in 10k w 16.7k w gnd 0v 60 w uncl deem v ref 2.4v 25k w 0042a-10.eps figure 4 videem1 ron of the transistor gate is 10k w . 1 125 m a 6 m /2 m 10 m /2 m videem1 0042a-11.eps figure 5 videem2 / 22khz ron of the transistor gate is 10k w . 1 125 m a 6 m /2 m 10 m /2 m videem2/22khz v dd 5v 100 m /2 m 60 m /2 m 22khz 0042a-12.eps figure 6 vid in v ref 2.4v vid in 6.5k w 10k w 85 m a gnd 0v 1 0.5pf + 0042a-13.eps figure 7 v dd 9v audio pk out peak detector 5k w 3.4v clamp 1 1 0042a-14.eps figure 8 pk out STV0042A 12/24
pin internal circuitry (continued) fc l, fc r ivar is controlled by the peak det audio level max. 15 m a (1v pp audio). fc l fc r 1 1 v dd 9v ivar 0042a-15.eps figure 9 vol out r, vol out l audio output with volume and scart driver with +12db of gain for up to 2v rms . the opamp has a push-pull output stage. audio 2.4v bias 30k w gnd 0v 30k w vol out r vol out l 15k w 4.8v 0042a-16.eps figure 10 s2 out l, s2 out r same as above but with gain fixed at +6db. audio 2.4v bias 20k w gnd 0v s2 out l s2 out r 20k w 0042a-17.eps figure 11 1 2.4v i ref 0042a-20.eps figure 14 s2 rtn l, s2 rtn r 4.8v bias voltage is the same as the bias level on the audio outputs. fm in the otherinput for each channelis internallybiased in the same way via 10k w to the 2.4v v ref . i ref the optimum value if i ref is 50 m a 2% so an external resistor of 47.5k w 1% is required. 50 m a 1 s2 rtn l s2 rtn r 4.8v 25k w 0042a-18.eps figure 12 50 m a 1 fm in 2.4v 10k w 1 10k w left channel right channel 50 m a 0042a-19.eps figure 13 scl this is the input to a schmitt input buffer made with a cmos amplifier. sda 24 m /4 m 205 w esd 600 m /2 m gnd 0v 0042a-22.eps figure 16 sda input same as above. output pull down only : relies on external resistor for pull-up. scl 24 m /4 m 205 w esd 0042a-21.eps figure 15 u75 l u75 r i2 i1 0042a-23.eps figure 17 u75 l, u75 r i1 - i2 = 2 x audio / 18k w .eg1v pp audio : 55 m a. the are internal switches to match the audio level of the different standards. STV0042A 13/24
750 m a 460 w xtl gnd 0v 2 3 2 500 m a 5pf 460 w 3 750 m a 0042a-24.eps figure 18 cpump l cpump r vco input 1 m a 1 m a loop filter tracking 100 m a 100 m a dig synth 0042a-25.eps figure 19 det l det r i1 i2 0042a-26.eps figure 20 pin internal circuitry (continued) xtl cpump l, cpump r an offset on the pll loop filter will cause an offset in the two 1 m a currents that will prevent the pll from drifting-off frequency. det l, det r i2 - i1 = f (phase error). amplk l, amplk r, agc l, agc r i2 and i1 from the amplitude detecting mixer. v ref 2.4v amplk l amplk r 10k w i1 2 i2 160 m a 5 m a agc l agc r to vca 0042a-27.eps figure 21 v ref the 400 m a source is off during stand-by mode. 4 vbg 1.2v v ref (2.4v) 10k w 10k w gnd 0v 400 m a 0042a-28.eps figure 22 1 v ref 2.4v sumout 50k w 100 m a 49k w 49k w audio 0042a-29.eps figure 23 1 v ref 2.4v pk in 67k w 100 m a to peak det 0042a -30.eps figure 24 sumout pk in v 12v doubled bonded (two bond wires and two pads for one package pin) : - one pad is connected to all of the 12v esd and video guard rings. - the second pad is connected to power up the video block. v gnd doubled bonded : - one pad is connected to power-up all of the video mux and i/o. - the second pad is only as a low noise gnd for the video input. v dd 5v, gnd 5v connected to xtl oscillator and the bulk of the cmos logic and 5v esd. STV0042A 14/24
pin internal circuitry (continued) a gnd l doubled bonded : - one pad connected to the left vco, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. - the second pad is connected to both agc amps and the deemphasis amplifiers, frequency syn- thesis and fm deviation selection circuit for both channels. a 12v doubled bonded : - one pad connected to the esd and guard ring. - the second pad is connected to the main power for all of the audio parts. a gnd r boubled bonded : - one pad connected to the right vco, dividers, mixers and guard ring. the guard connection is star connected directly to the pad. - the second pad is connected to the bias block, audio noise reduction, volume, mux and esd. v 12v v gnd video pads v dd 5v gnd 5v digital pads 205 w a gnd l a 12v a gnd r audio pads + bip 12v - substrate dzpn1 dzpn1 dzpn1 bip 10vpl vpp vmm 0042a-31.eps figure 25 a third bond wire on this pin is connected directly to the die pad (substrate). STV0042A 15/24
i 2 c protocol 1) writing to the chip s -start condition p -stop condition chip addr - 7 bits. 06h w -write/read bit is the 8th bit of the chip address. a -acknowledge after receiving 8 bits of data/adress. reg addr address of register to be written to, 8 bits of which bits 3, 4, 5, 6 & 7 are 'x' or don't care ie only the first 3 bits are used . data 8 bits of data being written to the register. all 8 bits must be written to at the same time. reg addr/a/data/a can be repeated, the write process can continue untill terminated with a stop condition. if the reg addr is higher than 07 then iic protocol will still be met (ie an a generated). example : s06w a00a55a01a8f a p 2) reading from the chip when reading, there is an auto-incrementfeature. this means any read command always starts by reading reg 8 and will continue to read the following registers in order after each acknowledge or until there is no acknowledge or a stop. this function is cyclic that is it will read the same set of registers without re-addressing the chip. there are two modes of operation as set by writing to bit 7 of register 0. read 3 registers in a cyclic fashion or all 5 registers in a cyclic fashion. note only the last 5 of the 11 registers can be read. reg0 bit 7 = l ? start / chip add / r / a / reg 8 / a/ reg 9 / a / reg 0a / a / reg 8 / a / reg 9 / a / reg 0a /... / p / reg0 bit 7 = h ? start / chip add / r / a / reg 8 / a / reg 9 / a / reg 0a / a / reg 7 / a / reg 6 / a / reg 8 / a / reg 9 / a / reg 0a / a / reg 7 / a / reg 6 / ... / p / control registers reg 0 write only bit (default 00 hex ) 0 l select 5 bits audio volume control 00h = mute 1 l select 5 bits audio volume control 01h = -26.75db 2 l select 5 bits audio volume control : : : : : 3 l select 5 bits audio volume control 1.25db steps up to 4 l select 5 bits audio volume control 1fh = +12db 5 l not to be used 6 l audio mux switch k3 - anrs select (l = no anrs, h = anrs) 7 l l = read 3 registers, h = read 5 registers reg 1 write only bit (default 00 hex ) 0 l select video gain bits 1 l select video gain bits 00h = 0db 2 l select video gain bits 01h = +0.202db 3 l select video gain bits 02h = +0.404db 4 l select video gain bits n = + 0.202 db * n 5 l select video gain bits 3fh = + 12.73 db 6 l selected video invert (h = inverted, l = non inverted) 7 l video deemphasis 1 / video deemphasis 2 (l : v id de-em 1) STV0042A 16/24
reg 2 write only bit (default f7 hex ) 0 h select video source for scart 1 o/p 1 h select video source for scart 1 o/p 2 h select video source for scart 1 o/p 3 l select 4.000mhz or 8.000mhz clock speed (l = 8mhz) 4 h select audio source for volume output (switch k1) 5 h select audio source for volume output (switch k1) 6 h select left/right/stereo for volume output 7 h select left/right/stereo for volume output reg 3 write only bit (default f7 hex ) 0 h select video source for scart 2 o/p 1 h select video source for scart 2 o/p 2 h select video source for scart 2 o/p 3 l video deemphais 2 / 22khz (h : 22khz) 4 h select audio source for scart 2 output (switch k5) 5 h select audio source for scart 2 output (switch k5) 6 h audio deemphasis select (switch k2) 7 h audio deemphasis select (switch k2) reg 4 write only bit (default bf hex ) 0 h not to be used 1 h not to be used 2 h not to be used 3 h stand-by or low power mode (h = low power) 4 h not to be used 5 h not to be used 6 l not to be used 7 h not to be used reg 5 write only bit (default b5 hex ) 0 h fm deviation selection -- default value for 50khz modulation 1 l fm deviation selection 2 h fm deviation selection 3 l fm deviation selection 4 h fm deviation selection 5 h fm deviation selection (l = double the fm deviation) 6 l not to be used 7 h not to be used reg 6 write/read bit (default 86 hex ) 0 l status of i/o 1 h select data direction of i/o 1 ( h = output) 2 h select frequency synthesizer 1 off/on (l = off) 3 l select frequency synthesizer 2 off/on (l = off) 4 l select rf source (l = off) to fm det 1 5 l select rf source (l = off) to fm det 2 6 l select frequency for pll synthesizer - lsb (bit 0) of 10-bit value 7 h select frequency for pll synthesizer - bit 1 of 10-bit value control registers (continued) STV0042A 17/24
reg 7 write/read bit (default af hex ) 0 h select frequency for pll synthesizer - bit 2 of 10-bit value 1 h select frequency for pll synthesizer 2 h select frequency for pll synthesizer 3 h select frequency for pll synthesizer 4 l select frequency for pll synthesizer 5 h select frequency for pll synthesizer 6 l select frequency for pll synthesizer 7 h select frequency for pll synthesizer - bit 9, msb (10th bit) of 10-bit value reg 8 read only bit 0 subcarrier detection (det 1) (l = no subcarrier) 1 not used 2 read frequency of watchdog 1 - lsb (bit 0) of 10-bit value 3 read frequency of watchdog 1 - bit 1 of 10-bit value 4 subcarrier detection (det 2) (l = no subcarrier) 5 not used 6 read frequency of watchdog 2 - bit 0 of 10-bit value 7 read frequency of watchdog 2 - bit 1 of 10-bit value reg 9 read only bit (default af hex ) 0 read frequency of watchdog 1 - bit 2 of 10-bit value 1 read frequency of watchdog 1 2 read frequency of watchdog 1 3 read frequency of watchdog 1 4 read frequency of watchdog 1 5 read frequency of watchdog 1 6 read frequency of watchdog 1 7 read frequency of watchdog 1 - bit 9, msb (10th bit) of 10-bit reg 0a read only bit 0 read frequency of watchdog 2 - bit 2 of 10-bit value 1 read frequency of watchdog 2 2 read frequency of watchdog 2 3 read frequency of watchdog 2 4 read frequency of watchdog 2 5 read frequency of watchdog 2 6 read frequency of watchdog 2 7 read frequency of watchdog 2 - bit 9, msb (10th bit) of 10-bit control registers (continued) STV0042A 18/24
video mux truth tables register 2 <0:2> ? scart 1 video output control register 3 <0:2> ? scart 2 video output control the truth table for the three scart outputs are the same. register 2/3 video output bit<2> 0 0 0 0 1 1 1 1 bit<1> 0 0 1 1 0 0 1 1 bit<0> 0 1 0 1 0 1 0 1 baseband video de-emphasized video normal video not to be used scart 2 return not to be used nothing selected high z or low power (default) audio mux truth tables register 2 switch k1/audio source selection for volume output bit <5> 0 1 0 1 bit <4> 0 0 1 1 a c b - volume output audio deemphasis (k2 switch o/p) scart 2 return not to be used high z or low power (default) register 3 switch k2/audio deemphasis bit <7> 0 1 0 1 bit <6> 0 0 1 1 a c b b audio deemphasis no deemphasis not to be used 50 m s 75 m s (default) register 0 switch k3 & k4 bit <6> 0 1 x x bit <5> x x 0 1 a b a b anrs i/o select noise reduction off noise reduction on (default) not to be used not to be used register 3 switch k5/audio source selection for scart 2 bit <5> 0 1 0 1 bit <4> 0 0 1 1 c a b - aux audio output pll output not to be used audio deemphasis (k2 switch o/p) high z or low power state (default) register 2 left / right / stereo on volume output bit <7> 0 1 1 bit <6> 0 0 1 mono left / channel 1 mono right / channel 2 stereo left & right (default) control registers (continued) STV0042A 19/24
register 5 : fm deviation selection 43210 selected nominal carrier modulation bit 5 = 0 bit 5 = 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 do not use do not use do not use cal. set. (2v) 592khz 534khz 484khz 436khz 396khz 358khz 322khz 292khz 266khz 240khz 218khz 196khz 179khz 161khz 146khz 122khz 120khz 109khz 98khz 89khz 78khz 71khz 65khz 58khz 53khz 48.6khz 43.8khz 39.6khz cal : do not use = 0.3373v offset on vco cal : do not use = 0.3053v offset on vco cal : do not use = 0.2763v offset on vco calibration setting (1v offset on vco) 296khz modulation 267khz modulation 242khz 218khz 198khz 179khz 161khz 146khz 133khz 120khz 109khz 98.3khz 89.7khz 80.9khz 73.1khz 66.0khz 60.0khz 54.4khz = default power up state 49.1khz 44.3khz 39.8khz 35.9khz 32.4khz 29.1khz 26.7khz 24.3khz 21.9khz 19.7khz example : default power up state 54.4khz ? 54.4khz. register 1 bit <7> register 3 bit <3> video deemphasis/22khz 0 0 1 1 0 1 0 1 deemphasis 1 (default) deemphasis 1 + 22khz (pin 13) deemphasis 2 deemphasis 2 fm demodulation software routine control registers (continued) with the STV0042A circuit, for each channel, three steps are required to acheive a fm demodulation : -1 st step :to set the demodulation parameters : ? fm deviation selection, ? subcarrier frequency selection. -2 nd step : to implement a waiting loop to check the actual vco frequency. -3 rd step :to close the demodulationphase locked loop (pll). refering to the fm demodulation block diagram (page 12), the frequency synthesis block is com- mon to both channels (left and right) ; consequently two completesequenceshave to be done one after the other when demodulating stereo pairs. detailed description conventions : - r = stands for register - b = stands for bit example : r05 b2 = register 05, bit 2 for clarity, the explanations are based on the fol- lowing example : stereo pair 7.02mhz/l 7.20mhz/r, deviation 50khz max. STV0042A 20/24
1st step (left) : setting the demodulation parameters a. the fm deviation is selected by loading r5 with the appropriate value. (see r5 truth table). nb : very wide deviations (up to 592khz) can be accomodated when r5 b5 is low. corresponding bandwidth can be calculated as follows : bw 2 (fm deviation + audio bandwidth) bw 2 (value given in table + audio bandwidth) in the example : r5bits 76543210 xx1 1 0 11 0 b. the subcarrier frequency is selected by launching a frequencysynthesis(the vcoisdriven to thewanted frequency).this operation requires two actions : - to connect the vco to the frequency synthesis loop. refering to the fm block diagram (page 12): ? sw4 closed ? r6 b2 = h ? sw3 to bias ? r6 b4 = l ? sw2 to bias ? r6 b3 = l ? sw1 opened ? r6 b5 = l - to load r7 and r6 b6 b7 with the value corre- sponding to the left channel frequency. this 10 bits value is calculated as follows : subcarrier frequency = coded value x 10khz (10khz is the minimum step of the frequency synthesis function) . considering that the tunning range is comprised between 5 to 10mhz, the coded value is a number between 500 and 1000 (2 10 = 1024) then 10 bits are required. example : 7.02mhz = 702 x 10khz 702 ? 1010 1111 10 ? af + 10 r7 is loaded with af and r6 b6 : l, r6 b7 : h. the table 1 gives the setting for the most common subcarrier frequencies. 2 nd step (left) : vco frequencychecking (vco) this secondstepis actually a waiting loop in which the actualrunning frequencyof the vco is measured. to exit of this loop is allowed when : subcarrier frequency - 10khz measured frequency sub- carrier frequency+10khz( 10khz is the maximum dispersion of the frequencysynthesisfunction). inpractice,r8 b2 b3 and r9 are readand compared to the value loaded in r6 b6 b7 and r7 1 bit. note : the duration of this step depends on how large is frequency difference between the start frequency and the targeted frequency. typically : - the rate of change of the vco frequencyis about 3.75mhz/s (c pump =10 m f) - in addition to this settling time, 100ms must be added to take into account the sampling period of the watchdog. 3 rd step (left) the fm demodulationcan be startedbyconnecting the vco to the phase locked loop (pll). in practice : - sw3 closed ? r6 b4 = h - sw4 opened ? r6 b2 = l after this sequence of 3 steps for left channel, a similar sequence is needed for the right channel. note : in thesequenceforthe right,thereisno needtoagain select the fm deviation (once is enoughfor the pair). general remark before to enable the demodulated signal to the audio output, it is recommandedto keep the muting and to check whether a subcarrier is present at the wanted frequency. such an informationis available in r8 b0 and r8 b4 which can be read. two different strategies can be adoptedwhen ena- bling the output : - either both left and right demodulatedsignals are simul- taneouslyauthorizedwhen both channelare ready. - or while the right channel sequence is running, the already ready left signal is sent to the left and right outputsandtherealstereosoundl/risoutputwhen both ch annels are ready. this second option gives sound a few hundredsof ms before the first one. table 1 : frequency synthesis register setting for the most common subcarrier frequencies subcarrier freq. (mhz) register 7 (hex) register 6 bit 7 bit 6 5.58 8b 1 0 5.76 90 0 0 5.8 91 0 0 5.94 94 1 0 6.2 9b 0 0 6.3 9d 1 0 6.4 a0 0 0 6.48 a2 0 0 6.5 a2 1 0 6.6 a5 0 0 6.65 a6 0 1 6.8 aa 0 0 6.85 ab 0 1 7.02 af 1 0 7.20 b4 0 0 7.25 b5 0 1 7.38 b8 1 0 7.56 bd 0 0 7.74 c1 1 0 7.85 c4 0 1 7.92 c6 0 0 8.2 cd 0 0 8.65 d8 0 1 fm demodulation software routine (continued) STV0042A 21/24
STV0042A c64 1.5nf r58 43k w v ccv q1 bc547 tv scart 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 11 12 13 14 15 21 29 30 36 37 38 40 31 32 33 34 35 39 41 42 28 27 26 25 24 23 22 jp5 jp8 jp10 jp9 r57 24k w c63 220nf r54 3.3k w c62 8.2nf r55 1.5k w c61 1.5nf q4 bc557 r56 10k w v cca jp7 r53 43k w c60 1.5nf c58 100nf r50 47.5k w 1% c50 10 m f 16v + r37 560k w c45 100nf v cca r51 560k w r40 180k w c47 22pf c48 22pf r41 82k w c46 2.7nf r39 27k w c40 470 m f 16v + c43 100nf r36 560k w c42 100nf c39 2.7nf r34 27k w r33 180k w c38 22pf c37 22pf r32 82k w c41 10 m f 16v + v dd c29 22pf jp2 1 2 3 4 jp6 c66 47pf j10 5v sda scl gnd 1 1 i/o clock input j9 j8 1 1 5v gnd j12 j11 l1 22 m h + c31 220 m f 16v c30 100nf v dd 1 1 12v gnd j14 j13 l2 22 m h + c33 220 m f 16v c32 100nf v ccv + c35 220 m f 16v c34 100nf v cca 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j1 j6 r j5 l j4 v r2 68 w r3 470 w c2 2.2 m f c3 2.2 m f jp11 v ccv q2 bc547 r4 470 w v ccv jp1 c56 100nf c23 8.2nf c24 27pf r17 470 w r18 1k w l4 47 m h c25 100pf r48 75 w c26 10 m f 16v j7 tuner input c12 100pf r9 5.1k w c14 150pf r14 5.6k w + c13 10 m f 16v r11 1.5k w r10 10k w r12 1.8k w r13 10k w + c15 10 m f 16v c5 2.2 m f vcr/decoderscart 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j2 r5 68 w c6 2.2 m f c8 2.2 m f c7 2.2 m f c11 8.2nf r16 1k w 3 2 1 tdk filter sel5618 r15 1k w r6 75 w c4 220nf optionally : a second video deemphasis network r13, r12, c15, r14, c14 is shown for 525 lines systems. sel5618 : 5mhz lpf made by tdk / japan c65 47pf 4mhz or 8mhz crystal r60 1.2m w c66 100nf c65 100nf r59 1.2m w 0042a-32.eps typical application (with 2 video deemphasis network) STV0042A 22/24
STV0042A c64 1.5nf r58 43k w v ccv q1 bc547 tv scart 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 11 12 13 14 15 21 29 30 36 37 38 40 31 32 33 34 35 39 41 42 28 27 26 25 24 23 22 jp5 jp8 jp10 jp9 r57 24k w c63 220nf r54 3.3k w c62 8.2nf r55 1.5k w c61 1.5nf q4 bc557 r56 10k w v cca jp7 r53 43k w c60 1.5nf c58 100nf 47.5k w -1% c50 10 m f 16v + r37 560k w c45 100nf v cca r51 560k w r40 180k w c47 22pf c48 22pf r41 82k w c40 470 m f 16v + c43 100nf r36 560k w c42 100nf r33 180k w c38 22pf c37 22pf r32 82k w c41 10 m f 16v + v dd c29 22pf jp2 1 2 3 4 jp6 c66 47pf j10 5v sda scl gnd 1 1 i/o clock input j9 j8 1 1 5v gnd j12 j11 l1 22 m h + c31 220 m f 16v c30 100nf v dd 1 1 12v gnd j14 j13 l2 22 m h + c33 220 m f 16v c32 100nf v ccv + c35 220 m f 16v c34 100nf v cca 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j1 j6 r j5 l j4 v r2 68 w r3 470 w c2 2.2 m f c3 2.2 m f jp11 v ccv q2 bc547 r4 470 w v ccv jp1 c56 100nf c23 8.2nf c24 27pf r17 470 w r18 1k w l4 47 m h c25 100pf r48 75 w c26 10 m f 16v j7 tuner input c12 100pf r9 5.1k w + c13 10 m f 16v r11 1.5k w r10 10k w c5 2.2 m f vcr/decoder scart 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 j2 r5 68 w c6 2.2 m f c8 2.2 m f c7 2.2 m f c11 8.2nf r16 1k w 3 2 1 tdk filter sel5618 r15 1k w r6 75 w c4 220nf optionally : a second video deemphasis network r13, r12, c15, r14, c14 is shown for 525 lines systems. sel5618 : 5mhz lpf made by tdk / japan c65 47pf 4mhz or 8mhz crystal r60 1.2m w c66 100nf c65 100nf r59 1.2m w 22khz tone 27k w 2.7nf r50 75/j17 8.2nf 4.7k w 36k w 4.7k w 4.7k w 4.7k w 36k w 4.7k w 8.2nf 27k w 2.7nf 0042a-33.eps typical application (with 22khz tone and three audio de-emphasis 50 m s, 75 m s, j17) STV0042A 23/24
a1 be b1 d 22 21 42 1 la e1 a2 c e1 e e2 gage plane .015 0,38 e2 e3 e sdip42 pmsdip42.eps package mechanical data 42 pins - plastic shrink dip dimensions millimeters inches min. typ. max. min. typ. max. a 5.08 0.200 a1 0.51 0.020 a2 3.05 3.81 4.57 0.120 0.150 0.180 b 0.38 0.46 0.56 0.0149 0.0181 0.0220 b1 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.0090 0.0098 0.0150 d 36.58 36.83 37.08 1.440 1.450 1.460 e 15.24 16.00 0.60 0.629 e1 12.70 13.72 14.48 0.50 0.540 0.570 e 1.778 0.070 e1 15.24 0.60 e2 18.54 0.730 e3 1.52 0.060 l 2.54 3.30 3.56 0.10 0.130 0.140 sdip42.tbl information furni shed is believed to be accurate and reliable. however, sgs-thomson micr oelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise und erany patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this pu blication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1997 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - canada - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV0042A 24/24

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